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" ... Say thank you! “Reward your referrers and make it a fun surprise! The minute someone passes your name or business along, respond with your own unique brand of thank you. This could be a bottle of wine delivered, a card with a handwritten note, an email with a coupon for a coffee—I often drop off or mail bottles of Tabasco to those I appreciate because of a story I always tell when speaking at conferences and I also share it in my book, The Little Red Stick: What Gets Measured Gets Done. If you can find something that is on-brand with your business, you will create loyalty from a happy surprise and a memory that will keep you top of mind when it comes to your specialty.” ... "
" ... Synopsys claims its DSO.ai tool can dramatically accelerate, enhance and reduce the costs involved with something called place-and-route. Place-and-Route is an integral stage in the design of circuit boards, ICs, and FPGAs (Field Programmable Gate Arrays). Just as it sounds, place-and-route (sometimes called PnR or Floorplan Placement) referrers to the placement of logic and IP blocks, and the routing of the traces and various interconnects designed to join them all together. Although various criteria are also top of mind throughout other stages in the design cycle of a chip, power, frequency, latency and silicon area are all important considerations during place-and-route, within the strict confines of the specific manufacturing process being employed. Synopsys’ DSO.ai optimizes and streamlines this process using the iterative nature of artificial intelligence and machine learning, to turn what used to take dozens of engineers weeks or potentially months, into something a junior engineer can do on their own in just days. DSO.ai iterates on the floorplan and layout of a chip, and learns from each iteration, fine tuning and optimizing the chip within its design parameters along the way. Not only does this positively impact the economics and success rate of chip design, but results in a fundamental shift in design resources and methodology, which liberates engineers that may have been previously occupied by place-and-route duties to address and be more creative in other aspects of cutting-edge chip design. ... "