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" ... As we have mentioned before, Intel is also innovating on packaging and interconnects that give it the flexibility to build things like Intel's Lakefield processors. In the future, Intel expects to use TSV (through substrate via) hybrid bonding to reduce the pitch between dies to reduce 5x (from 50 um to 10um), which allows for smaller, simpler circuits as well as lower power and capacitance. Intel has also previously disclosed packaging technologies like Co-EMIB for allowing the stacking of compute and memory dies both horizontally (2D) and vertically (3D) on the same chip, allowing for much larger chips than could be produced monolithically. In addition to Co-EMIB, Intel has also previously talked about ODI, which it is still clearly pursuing, which allows for a tighter 3D integration of dies than what Foveros offers with direct power delivery and higher bandwidth interconnects. Intel is also expected to bring a high-performance follow-on to Lakefield with Alder Lake, which is expected to combine Intel's Golden Cove and Gracemont cores together into a higher performance hybrid architecture. However, this is not the limit of what Intel can do with packaging and interconnects, as the company is planning to us optical IO in the future with ultra-high bandwidth 1 Tbps per fiber. Intel is expecting to deliver 6x better density than PCIe Gen 6 (which is not expected to be finalized until 2021). Intel's optical IO is also expected to have 50% better power efficiency than PCIe Gen 6 and have comparable latency to electrical IO. ... "
" ... Combining a Super MIM capacitor, which offers a five-fold increase in MIM capacitance, with redesigned FinFET, SuperFin will lower resistance and allow more current through the channel, which it claims will boost certain functions that require maximum performance, while vdroop will be reduced too. ... "